The disclosure relates to a method of fabricating an integrated circuit device, and more particularly, to a method of fabricating an integrated circuit device, the method including an exposure process using i-line (365 nm) irradiation.
As downscaling and high integration of integrated circuit devices rapidly progresses, there is a need for techniques allowing improvement in dimensional precision of a pattern desired to be formed when the pattern is formed by using a large-area positive tone patterning process. In particular, to prevent residual defects caused by unwanted photoresist residues remaining in an exposed region in a large-area positive tone patterning process, there is a need to develop a process of forming a pattern by using an exposure process.